1. Field of the Invention
The present invention generally relates to synchronizing (sync.) signal detecting circuits and, more particularly, to a synchronizing signal detecting circuit which can be suitably applied to display units for computers, for example.
2. Description of the Prior Art
In some computers, a reference pulse R is inserted into a back porch of a pedestal portion of a synchronizing signal in a video signal output to the display unit as shown in FIG. 1, and the inserted reference pulse R is used to make a contrast of the display unit constant. When a predetermined signal such as the reference pulse R or the like is inserted into the back porch, if a length S of the sync. chip portion is increased too much, a length of the pedestal portion (i.e., a length F of a front porch and a length B of the back porch) is reduced relatively. There is then the risk that the reference pulse R cannot be inserted into the back porch. For this reason, in order to prevent the length of the back porch from being reduced too much, a conventional synchronizing signal detecting circuit controls the length of the sync. chip portion so that the length of the sync. chip portion corresponds to a horizontal scanning frequency (horizontal scanning frequencies are different depending upon types of computers).
FIG. 2 of the accompanying drawings shows in block form a circuit configuration of an example of a synchronizing signal detecting circuit according to the prior art.
Referring to FIG. 2, a synchronizing separating circuit 31 operates to separate and detect a synchronizing signal from an input signal and outputs a detected pulse. The detected pulse from the synchronizing separating circuit 31 is supplied to a pulse width adjusting circuit 32 and a frequency detecting circuit 33. The frequency detecting circuit 33 operates to detect a frequency of the detected pulse input thereto (i.e., the frequency of the horizontal synchronizing signal) and supplies a signal corresponding to the detected frequency to the pulse width adjusting circuit 32. The pulse width adjusting circuit 32 operates to adjust the width of the detected pulse input thereto from the synchronizing separating circuit 31 in response to the signal input thereto from the frequency detecting circuit 33. Thus, when the frequency becomes higher, the width of the detected pulse is reduced more, while when the frequency become lower, the width of the detected pulse is increased more.
Although the length S of the sync. chip portion of the video signal output from the computer substantially corresponds to a horizontal scanning frequency (when the frequency is higher, the length S of the sync. chip is selected to be shorter, while when the frequency is lower, the length S of the sync. chip portion is selected to be longer), depending on the types of computers, it is frequently observed that the length S of the sync. chip portion is set to be short as compared with those of other types of the computers having the same horizontal scanning frequency. In other words, the length S of the sync. chip portion is set to be short even though the frequency is comparatively low.
In such case, according to the conventional synchronizing signal detecting circuit, the length of the sync. chip portion is adjusted so as to become longer in response to the horizontal scanning frequency. Consequently, the length B of the back porch is reduced as shown by a phantom in FIG. 3, for example. There is then the risk that the reference pulse R cannot be inserted into the back porch.